DLS

DLS is a time-driven event-based multi-delay 3-value digital logic simulator.

- Time-driven means that the circuit time is advanced forward based on a user-specified target speed, which is measured in circuit nanoseconds per real second (ns/s). The simulation will always advance to a new state if there are pending signals in the circuit's queue. This means that even unstable or asynchronous circuits can be correctly simulated.
- Event-based means that a gate is simulated only if one of its inputs changes value. Otherwise the previous output is considered valid and used as input to all connected gates/components.
- Multi-delay means that each build-in gate/component type has its own propagation delay which is always an integer greater than or equal to 1.
- 3-value means that in addition to logic levels 0 and 1 there's an extra logic value (U for Undefined) which is used as both Z (high impedance) and X (undefined) signals, depending on its origin.